In further another aspect of the present invention, there is provided a scrambling code generating apparatus of a downlink transmitter in a UMTS mobile communication system, which uses one primary scrambling code for separation of base stations and multiple secondary scrambling codes for channel separation, the apparatus including: a first m-sequence generator for generating a first m-sequence; a second m-sequence generator for generating a second m-sequence; a first summer for adding the first and second m-sequences to generate the primary scrambling code; a plurality of masking sections, each of the first masking sections for shifting the first m-sequence; and a plurality of second summers, each of the second summers for adding one of the shifted first m-sequences with the second m-sequence, the output of the second summers generating the multiple secondary scrambling codes.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:.
A preferred embodiment of the present invention will be described below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
A gold code used herein as a scrambling code is generated through binary adding of two distinct m-sequences. Assuming that the two m-sequences each having a length L are defined as m 1 t and m 2 t , respectively, a set of gold codes may comprise L distinct gold sequences with good correlation characteristic with one another.
The set of gold codes can be expressed by Equation 1. The embodiments of the present invention provide a generator for concurrently generating multiple gold sequences using the mask functions, and a method for efficiently dividing the set of gold sequences into a primary scrambling code set and a secondary scrambling code set to reduce the number of mask functions stored in the memory.
Here, when primary scrambling codes are used, there are five groups of secondary scrambling codes corresponding to the primary scrambling codes. Out of six m-sequence code groups, the first scrambling code group is used as primary scrambling codes and the remaining five scrambling code groups are used as secondary scrambling codes.
In this structure, if a cell base station uses its own primary scrambling code and secondary scrambling codes selected out of its own secondary scrambling codes group, then the selected secondary scrambling codes belonging to the secondary scrambling code group corresponding to the primary scrambling code will be used for downlink channel scrambling codes when orthogonal codes are not available with the primary scrambling code.
As shown in FIG. Here, the secondary scrambling codes are generated through application of mask functions to the primary scrambling codes. This method is adapted to a scrambling code group generator of a transmitter as illustrated in FIG. The values stored in each of the registers in the memory and the memory may change during every period of an input clock not shown. The first m-sequence generator generates a first m-sequence using the register memory and the adder which is a binary adder that adds the binary values from the registers 0 and 7 of the register memory and outputs the sum into the register The register 0 of the register memory sequentially outputs binary values that form the first m-sequence during every period of the input clock.
The masking sections to store mask code values k 1 i to k N i for generating cyclical shifts of the first m-sequence by a predetermined number of chips.
The resulting values are provided to the adders to , respectively. The second m-sequence generator generates a second m-sequence using the register memory and the adder which is binary adder that adds the binary values from the registers 0 , 5 , 7 and 10 of the register memory and outputs the sum into the register The register 0 of the register memory sequentially outputs binary values that form the second m-sequence during every period of the input clock.
The masking sections to store each mask code values s 1 i to s N i for generating cyclical shifts of the second m-sequence by a predetermined number of chips. Each of the m-sequence generators and generates an m-sequence according to the corresponding generator polynomial. The adders to add one bit generated from each of the masking sections to connected to the first shift register memory to one bit generated from the masking sections to corresponding to the masking sections to , respectively.
In other words, the output from the first masking section from the first group is added with the output from the first masking section from the second group and so on, until the output from the N-th masking section from the first group is added with the output from the N-th masking section from the second group.
Thus, each of the masking sections - in the first group has a corresponding masking section in the masking section s - of the second group. The outputs from the corresponding masking sections are added together in the adders - , respectively. That is, the individual masking sections have a conjugate on a one-to-one basis with respect to the first and second shift register memories and For example, the first masking section of the first shift register memory corresponds to the first masking section of the second shift register memory , the N-th masking section corresponding to the N-th masking section , and so on.
Between the two conjugate masking sections i. Here, the output signals of the summers to have an I-channel component. The delay to and delay the I-channel signals for a predetermined number of chips to generate respective Q-channel signals.
Now, a description will be given to an operation of the present invention as constructed above. Then, the first masking section masks the input values from the first upper shift register memory all 18 bits from 18 registers in the shift register memory with a mask function k 1 i i. The masking is concurrently processing in every masking sections - The N-th masking section masks the input values from the first upper shift registers with a mask function k N i i.
The N-th masking section masks the input values from the second lower shift registers with a mask function s N i i. The first masking section masks the input values from the register memory with a mask function s 1 i i. Each of the masking sections - masks the input values from the first shift register memory and outputs the masked value to the respective adders - Then, the adder adds the output bits from the 0-th registers of the first and second shift register memories and These generated output signals are immediately delayed at the delay The adder adds the output bits from the N-th masking sections and to generate I-channel signals, which are immediately fed into the delay The delay delays the I-channel signals output from the adder for a predetermined number of chips to generate Q-channel scrambling signals.
The adder adds the output bits from the first masking sections and to generate I-channel signals. These I-channel signals are immediately delayed for a predetermined number of chips at the delay Then, the 0-th and seventh register values of the first shift register memory are added at the summer and the added value is inputted to the seventeenth register, as the left-sided values are shifted to the right side by one and the utmost left-sided register is newly filled with the output value of the summer The 0-th, fifth, seventh, and tenth register values of the second shift register memory are added at the adder , the added value is inputted into the seventeenth register, as the left-sided values are shifted to the right side by one and the utmost left-sided register i.
This procedure is repeated to generate multiple scrambling codes. The receiver has only to use scrambling codes for a common control channel and a data channel assigned thereto and thus needs one primary scrambling code and one secondary scrambling code. The output of the adder is a primary scrambling code.
Then, the masking section masks the input values from the first shift register with a mask function k i i. The masking section masks the input values from the second lower shift register with a mask function s i i.
Then, the adder adds the output bits from the 0-th registers of the first and second shift register memories and to generate I-channel primary scrambling code signals.
These I-channel primary scrambling code signals are immediately delayed for a predetermined number of chips at a delay to generate Q-channel primary scrambling code signals.
The adder adds the output bits from the masking sections and to generate I-channel primary scrambling code signals, which are immediately delayed at a delay Then, the 0-th and seventh register values of the first shift registers are added at the adder , and the added value is output to the seventeenth register, as the left-sided values are shifted to the right side by one.
The 0-th, fifth, seventh and tenth register values of the second shift registers are added at the adder , and the added value is output to seventeenth register, as the left-sided values are shifted to the right side by one. The scrambling code generator of the first embodiment needs plurality of distinct mask functions stored in the masking sections in order to generate each secondary scrambling code, i. Accordingly, the structure of primary and secondary scrambling codes shown in FIG.
While the first embodiment masks both m-sequences m 1 t and m 2 t to generate scrambling codes, the second embodiment involves cyclic shift of the m-sequence m 2 t only other than m 1 l to generate scrambling sequences.
That is, this embodiment is well expressed by Equation 1. Here, with primary scrambling codes used, each of the secondary scrambling code sets corresponding to the primary scrambling codes is composed of M secondary scrambling codes. In this structure, if a cell uses one of the primary scrambling codes then secondary scrambling codes belonging to the secondary scrambling code group corresponding to the primary scrambling code will be used when the secondary scrambling codes need to be used.
Here, the secondary scrambling codes are generated through application of mask functions to the sequences in the first shift register memory. This method is adapted to a scrambling code generator of a transmitter as illustrated in FIG. The second m-sequence generator comprises a second register memory with registers 0 to 17 and an adder for adding the outputs of the registers 0 , 5 , 7 and The scrambling code generator shown in FIG.
The two m-sequence generators and generate respective serial output sequence bits according to each generation polynomials at every period of the input clock not shown.
The second embodiment of the present invention uses a gold code length of symbols to generate scrambling codes. Thus, the shift register memories and may be reset to the initial value when each of the register memories and outputs a sequence having a length of symbols.
The first m-sequence generator generates the first m-sequence using the register memory and the adder which is a binary adder that adds the binary values from the registers 0 and 7 of the register memory and outputs the sum into the register In the preferred embodiments of the present invention, each of the mask code values k 1 i to k N i creates a new sequence which is a first m-sequence cyclically shifted 1 to N times. Therefore, if the OVSF codes are allocated irregularly to the various signals having different chip rate under the procedure in the related art for generating and allocating the OVSF code, the interference between signal to signal occurs because the codes may not be orthogonal to one another.
If the transmitting device supporting single chip rate is expanded to support multiple chip rate, the interference between signal to signal does not occur among signals of same chip rate because of orthogonal property, but the interference between signal to signal among signals of different chip rates would increase, because the scrambling codes are different from one another and the orthogonal property cannot be sustained between channelization codes.
Accordingly, an object of the present invention is to solve at least the problems and disadvantages of the related art. An object of the present invention is to provide a method and system for transmitting data of multiple chip rates in a CDMA mobile communication system.
Another object of the present invention is to provide a method for allocating channelization codes in multiple code rates which discriminates the channel dedicated to each user signal having different code chip rates to minimize interference signal. A further object of the present invention is to provide a method of allocating channelization codes in multiple code rates which is designed to minimize interference according to the types of pulse shaping functions.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims. To achieve the objects and in accordance with the purposes of the invention, as embodied and broadly described herein, a method of allocating channelization codes for transmission of signals in multiple code rates in a mobile communication system includes generating a set of codes from OVSF codes; allocating OVSF codes as channelization codes for signals of a first chip rate; and allocating the generated set of codes as channelization codes for signals of a second chip rate, where the first chip rate is lower than the second chip rate.
The present invention may further comprise scrambling signals of the first chip rate and signals of the second chip rate with scrambling codes having a same chip rate and a same scrambling code sequence pattern. Here, the scrambling codes of the first chip rate are used for signals of both the first and second chip rates. In the above embodiment, the second chip rate is 2 y times the first chip rate, where Y is a positive integer.
If a pulse shaping function is rectangular, the set of codes are generated by finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero. Also, the set of codes are generated by finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero and which has point symmetry, if a pulse shaping function is symmetrical.
Moreover, the generated set of codes are allocated by dividing the generated set of codes into 2 y groups and selecting a group which causes the least interference to the signals of the first chip rate.
Accordingly, the present invention introduces a method for allocating channelization code and scrambling code in multiple code rates and a method and an apparatus for transmitting signal through multiple chip rates minimizing interference.
Particularly, the present invention is appropriate in an environment where various user signals having various chip rates exist in an overlaid carrier frequency band. In accordance with the present invention, many users signals that have various chip rates in overlaid frequency band can be transmitted with minimum interference between users, by way of allocating orthogonal spreading code in which the sum of bits for a period that is determined by the ratio of chip rates is canceled respectively, as channelization codes.
The invention will be described in detail with reference to the following drawings in which like reference numerals refer to line elements wherein:. Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Generally, the present invention allows transmission of signals in multiple code rates in mobile communication systems.
Particularly, the present invention allocates channelization codes in multiple chip rates for transmitting signals in multiple chip rates. In accordance with the present invention, a method of allocating channelization codes for multiple code rates is accomplished by allocating orthogonal spreading codes, in which the sum of channelization code bits for a period that is determined by the ratio of chip rates is minimized, respectively, as channelization codes of a system where the user signals having various chip rates exist.
The signal of each user is time-synchronized to preserve orthogonality of channelization codes. In the present invention, it is assumed that the signals of users may have different chip rates, but the chip rates are restricted as follows.
The allocation procedure of OVSF codes to the user signal of chip rate R 0 is same as the allocation procedure in the related art. The method of present invention for allocating channelization codes regarding chip rate will be explained by applying a transmitter and a receiver in CDMA communication systems.
The data signal b k t of user k is same as expressed by Equation 3, but the spreading signal a k t of user k is as follows. T f is the reciprocal of the highest chip rate in the systems. Thus, the data signal b k t of user k is spread by multiplying spreading signal a k t and all spread signals are transmitted through a common channel. The signal transmitted through channel s t is equal to that expessed by Equation 1.
The interference signal I k,i nT i of the output signal Z i nT i of receiver is as follows. Moreover, the pulse shaping function should be considered along with the conditions for channelization code a k,r. The pulse shaping function of FIGS. However, a pulse shaping function may have a longer duration than T c,k and will be considered below. In addition, two cases for the pulse shaping function are considered, namely a rectangular pulse and a symmetrical pulse.
First, the method of allocating OVSF code when the chip pulse function is rectangular wave will be explained. Therefore, the R k,j m in Equation 9 can be expressed more simply by the following equation. Equation 10 above shows the cross-correlation value of two codes a k,r and a i,r. If a signal which has a shorter chip duration than the chip rate is a i,r and a signal which has a longer chip duration is a k,r , the relationship between the chip period T c,k of the code a k,r and the chip period T c,j of the code a i,r can be established as follows.
At this time, for a duration of T c,k , the value of code a i,r is changed P k,j times while the value of code a k,r is changed once. Therefore, R k,j m in Equ.
The condition that the value of Equation 12 equals to zero for arbitrary a k,r is the condition that the sum of codes while the code a i,r changes P k,j times is zero. Therefore, for the index i of all other users who use higher chip rate than that of user k, the following equation must be satisfied.
Thereafter, the procedure of allocating the QOMCR codes generated as described above is same as the conventional procedure. That is, in the code tree, all descendant codes and ancestor codes of the code allocated to the other users with the same chip rate, and the codes allocated to the other users with the same chip rate are not used in the signals of same chip rate.
However, the code allocation is not affected by different chip rate code allocation. This means that the same OVSF codes can be allocated to multiple users if their chip rates are not the same. The method of generating and allocating OVSF code when the pulse shaping function is symmetrical function is next considered.
The symmetrical function is the function which is symmetrical to the center of pulse, i. The condition which makes R k,j m of Equation 9 zero is when the following is satisfied. To satisfy Equation 14, the Equations 15 and 16 should be satisfied. That is, if the pulse shaping function is a symmetrical function, find and allocate OVSF codes which satisfy both Equations 15 and The codes that satisfy the above conditions are C ch,2,1 and the descendant codes of C ch,2,1.
Here, the second chip rate is double the first chip rate and the carrier frequency of the signal of the first or second chip rate is the same. For example, the first chip rate and the second chip rate may be one of 3. Furthermore, the system of FIG. The operation of the transmitting device according to the present invention is as follows.
First, the transmitting device of present invention is characterized by using the same scrambling code for signals of different chip rates and using QOMCR code as channelization code for the signals of higher chip rates. Namely, if the first chip rate is lower than the second chip rate, OVSF code is allocated through conventional procedure for the signal of first chip rate and QOMCR code is allocated for the signal of second chip rate.
The signals of both chip rates are then scrambled with the complex number scrambling code of the signal of first chip rate. As shown in FIG. Particularly, in the code tree shown in FIG. However, the channelization code allocated to the channel of second chip rate may be allocated repeatedly to the channel of first chip rate, and vice versa. Thus, the first mixer and the second mixer in FIG. The third mixer and sixth mixer respectively scramble the signals of first chip rate and second chip rate using the complex number scrambling code of first chip rate.
Therefore, the present invention as described above minimizes the interference between the signals with different chip rates. The interference between the signals with the same chip rate is zero due to the orthogonality of OVSF codes. If the duration of pulse shaping function is equal to the chip duration, the interference between the signals with different chip rates would also be zero.
However, in WCDMA communication systems, the duration of pulse shaping function, which is root-raised cosine function, is not restricted to the chip duration. The duration of pulse shaping function is time restricted in the range of several ten times of the chip range. In consideration of these pulse shaping function, the interference between channels of first chip rate and second chip rate is as follows in Table 1 and Table 2.
In Tables 1 and 2, the conventional system refers to the transmitting device shown in FIG. In such system, the first chip rate signal is scrambled by the scrambling code with the first chip rate, and the second chip rate signal is scrambled by the scrambling code with the second chip rate. This means that the scrambling codes of first and second chip rate have different chip rates. However, in the present invention, the same scrambling code having the same chip rate and same scrambling code sequence pattern are used for both first and second chip rates.
The scrambling codes of the first chip rate, which is lower than the second chip rate, are used for both first and second chip rate signals. In the above Table 1, the values are normalized energy values where the energy of desired signal is adjusted to 1.
This is also true in other spread factors. Accordingly, in consideration of the pulse shaping filter of WCDMA system and in order to further reduce interference between channels of different chip rates, the present invention comprises spreading signal using OVSF code as channelization code of first chip rate, optimizing and using QOMCR code as channelization code of the second chip rate, and using a same complex number scrambling code for scrambling signals of both first chip rate and second chip rate.
Here, the complex number scrambling code of first chip rate is used as complex number scrambling code of second chip rate. Regarding the priority of the two groups, the second group is prior to the third if the interference of signals of first chip rate to signals of second chip rate is more of a critical factor than the interference of signals of second chip rate to signals of first chip rate.
Otherwise, the third group is prior to the second. The above allocation method for second chip rate signal is based on the result of computer simulation which is listed in Table 3. The spreading factor and OVSF index of the signals of second chip rate are denoted in the first and second columns in Table 3, respectively. The ratio of interference at Table. Thus, the fact that this ratio is less than 1 indicates the improvement of the present invention method because the method of present results in lower interference than that of the method in the related art.
In this case, the spreading factor of the first chip rate signal is 4, but the tendency would be maintained for other spreading factors. Here, the system in the related art refers to the transmitting device shown in FIG.
In such system of the related art, the first chip rate signal is scrambled by the scrambling code with the first chip rate and the second chip rate signal is scrambled by the scrambling code with the second chip rate.
In the present invention, the same scrambling code, i. In this system, the scrambling code of lower chip rate is also commonly used as the scrambling code for the two chip rate signals, and the OVSF code is used as the channelization code for signal of lower chip rate. In this way, data signals of multiple chip rate can be transmitted by one transmitter with low interference between signals. Up to now, the case in which the carrier frequencies of first chip rate and second chip rate are the same has been considered.
The case when the carrier frequencies of first chip rate and second chip rate are not the same will next be considered. Generally, the concept of the present invention can be applied equally to both cases when the carrier frequencies of first chip rate and second chip rate are same or different, unless the carrier frequency separation between the different chip rate is relatively small. Here, the scrambling code and channelization code allocation method for the first chip rate and second chip rate is the same with that of the same carrier frequency for first and second chip rate.
In FIG. The transmitter in FIG. The time-sync of two chip rate signals are maintained to preserve the orthogonality of OVSF codes. The method of present invention may be applied by examining a computer simulation results, in which the carrier angular frequency of first chip rate is different from that of second chip rate and the second chip rate is multiple of the first chip rate, and both the two signals are transmitted concurrently. Particularly, FIG. Referring to FIGS. In obtaining the interference level of the signal of second chip rate to the signal of first chip rate shown in FIGS.
The tendency above could be found in signals of all spreading factor and of all chip rates. Because there are numerous second chip rates which are multiple of integer of first chip rate, and numerous values of the angular frequency of first frequency and second frequency, the method for allocating channel code to first chip rate and second chip rate for all cases cannot each be described.
However, in analogous manner as described above, various applications and modifications of present invention can be made. In the present invention, the transmitter side is described, but the same idea of present invention should be applied to a receiver side since the receiver operation is inverse of transmitter operation.
For example, the descrambling code with lower chip rate should be used for descrambling code for lower chip rate and higher chip rate. Moreover, in the present system, various applications and modifications can be made to a case where more than 3 chip rates exists concurrently.
The present invention can be also applied to wireline communication link, optical fiber communication link, twisted copper wire communication link, coaxial cable communication link, and satellite communication link. As mentioned above, the present invention enhances the capacity of transmitting data of multiple chip rate in a CDMA mobile communication system by allocating channelization code and scrambling code in multiple code rate, thereby allowing a transmission of signals of multiple chip rates with minimized interference in the environment where various user signals exist in a overlaid carrier frequency band.
The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.
All rights reserved. Login Sign up. Search Expert Search Quick Search. Scrambling codes and channelization codes for multiple chip rate signals in CDMA cellular mobile radio communication system.
United States Patent A system and method for allocating channelization code and scrambling code in multiple code rates is disclosed. In the present invention, many user signals that have various chip rates in overlaid frequency band can be transmitted with minimum interference between users, by allocating orthogonal spreading code in which the sum of bits for a period that is determined by the ratio of chip rates is canceled respectively, as channelization codes.
Click for automatic bibliography generation. Seoul, KR. Download PDF Schotten et al. A method of allocating channelization codes for transmission of signals in multiple code rates in a mobile communication system comprising: generating quasi orthogonal muti chip rate QOMCR codes from orthogonal variable spreading factor OVSF codes; allocating OVSF codes as channelization codes for signals of a first chip rate; and allocating QOMCR codes as channelization codes for signals of a second chip rate, where said first chip rate is lower than the second chip rate.
A method of claim 1, further comprising scrambling signals of said first chip rate and signals of said second chip rate with scrambling codes having a same chip rate and a same scrambling code sequence pattern. A method of claim 2, wherein scrambling codes of the first chip rate are used for signals of both said first and second chip rates. A method of claim 1, wherein the second chip rate is 2 y times the first chip rate, where Y is a positive integer, and wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero, if a pulse shaping function is rectangular.
A method of claim 4, wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of two code bits results in a value of zero if the second chip rate is twice the first chip rate, and wherein generating QOMCR codes comprises finding codes from OVSF codes in which a combination of four code bits result in a value of zero if the second chip rate is four times the first chip rate. A method of claim 1, wherein the second chip rate is 2 y times the first chip rate, where Y is a positive integer, and wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero and which has point symmetry, if a pulse shaping function is symmetrical.
A method of claim 1, wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of 2 code bits result ill a value of zero if the second chip rate is twice the first chip rate, and wherein generating QOMCR codes comprises finding codes from OVSF codes in which a combination of four code bits result in a value of zero if the second chip rate is four times the first chip rate.
A method of claim 1, wherein the second chip rate is 2 y times the first chip rate, where Y is a positive integer, and wherein allocating QOMCR codes to the signals of the second chip rate comprises dividing the generated QOMCR codes into 2 y groups and selecting a group of QOMCR codes which causes the least interference to the signals of the first chip rate.
A method of claim 9, wherein allocating the second group to the signals of the second chip rate. A method of claim 11, wherein allocating to the signals of the second chip rate the fourth group as the channelization codes, and if the fourth group is unavailable, allocating the third group as the channelization codes if said spreading factor sf2 is not greater than , and otherwise allocating either one of the second or third group as channelization codes. A method of claim 12, wherein allocating the second group if an interference of signals of the first chip rate to signals of the second chip rate is more of a critical factor than an interference of signals of the second chip rate to signals of the first chip rate, and otherwise allocating the third group.
The method of claim 14, wherein the selected group of the generated QOMCR codes causes least interference to signals having the first chip rate. The method of claim 16, wherein the selected group of the generated QOMCR codes causes least interference to signals having the first chip rate.
A method of allocating channelization codes for transmission of signals in multiple code rates in a mobile communication system comprising: generating quasi orthogonal muti chip rate QOMCR codes from orthogonal variable spreading factor OVSF codes; allocating OVSF codes as channelization codes for signals of a first chip rate; allocating QOMCR codes as channelization codes for signals of a second chip rate, wherein the second chip rate is 2 y times the first chip rate where y is a positive integer; and scrambling signals of said first chip rate and signals of said second chip rate with scrambling codes of said first chip rate.
A method of claim 18, wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero, if a pulse shaping function is rectangular.
A method of claim 18, wherein generating QOMCR codes comprises finding codes from the OVSF codes in which a combination of 2 y code bits result in a value of zero and which has point symmetry, if a pulse shaping function is symmetrical. A method comprising: allocating a orthogonal variable spreading factor OVSF code as a channelization code for signals to have a first chip rate; and allocating a quasi orthogonal multi chip rate QOMCR code as a channelization code for signals to have a second clip rate, said second chip rate being higher than the first chip rate.
The method of claim 23, wherein determining the QOMCR code comprises determining codes from the OVSF codes in which a combination of code bits result in a value of zero. The method of claim 22, further comprising scrambling signals of said first chip rate and signals of said second chip rate with scrambling codes having a same chip rate and a same scrambling code sequence pattern. The method of claim 22, wherein scrambling codes of the first clip rate are used for signals of both said first and second chip rates.
The method of claim 22, wherein the second chip rate is 2 y times the first chip rate. Field of the Invention This invention pertains to the field of wireless digital communication systems, and more particularly, to a method and system for transmitting user signals having various chip rates over carrier frequency band by assigning a channelization code to each user signal.
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